Wednesday, September 12, 2007


***Forgive me for being a little technical (but I don't think I'm giving away any secrets...).

I mentioned a little while back that I would try and post a little bit about the research that I was doing all summer. As I've mentioned previously, I spent much of the summer doing research with a professor here in my department. Me and another fellow designed, simulated and laid out a PLL. I'm not going to go into detail much about what a PLL is, but I will try and explain some of the photos in the slide show below.

The first picture is the schematic of the buffered charge pump. It is made up of 3 op-amps and then maybe 15 other transistors. The second picture is of the layout of the buffered charge pump. The layout is a file that we send off to a fabrication company and they use it to make the chip according to our specifications. We have designed our chip in a 0.5 micron, 3-metal AMI process. The colorful layout file designates where all of the different poly-silicon layers, metal layers, diffusion layers, etc. are to be located. The big green areas in the buffered-charge pump picture above are capacitors.

The next picture is the schematic for a divider circuit. This circuit takes a high frequency wave (designed for 900 MHz) and divides it by 180, effectively taking the frequency down to a much slower 5 MHz. The circuit is pretty simply in that it is made up of a D-latch, a bunch of J/K flip-flops and a few inverters. The picture after the schematic is once again the layout for the divider circuit.

The next schematic is for the op-amp that we used throughout the design. The layout for the op-amp is also shown. The yellow squares that you can see speckling the layout are contacts between metal layers and the substrate. Every other circuit also has a ton of these contacts (placed mainly by hand) but the photos are zoomed too far out to be able to see them.

The next two circuits are of phase-frequency detectors (PFD). There are two different ones. The first one is a regular PFD and the second one is part of the original design of this PLL. We are having three chips manufactured. The first one has our unique design that we are testing, the second one has a basic PLL that we can use to compare against and the third chip is made up of individual components that we will be able to test individually once the chips are manufactured.

The next layout is of a voltage-controlled oscillator (VCO). This circuit also has a large inductor that is not shown. The layout of the VCO buffer is also shown. The area on the left of this picture is a 20 k-ohm resistor. The schematic following the the buffer is of the full chip. As a nod to the peaceful co-habitation of world religions, the different circuit symbols are religious symbols (i.e. the VCO is the yin yang, the divider is an ankh, the charge pump is a star and crescent and the PFD is a cross).

The final three pictures are photos of the full chips that were sent away for fabrication.. The big yellow and green spiral is a 9 nH inductor for the VCO (the yellow layer is the uppermost metal layer). The pad-ring which circles around the outside of the chip is also shown. This is where microscopic gold wires will connect to the circuit. Just for measurement purposes, the full chip shown is only 1.5 mm x 1.5 mm. You might be able to pick out some of the other circuit components that were shown earlier - most of the full circuits are less than 100 microns squared.

We sent the chips off for fabrication (we'll be getting 5 copies of each chip for a total worth of more than $15,000) and we should be getting them back in mid-November. Then we will test them and see whether or not our design successfully does what our simulations showed us it would.

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